The present invention relates to a circuit for the (full-wave) rectification and integration of an alternating input signal, that is, a signal which can assume positive and negative amplitudes relative to a reference.
In devices for detecting alternating signals greatly affected by noise, which are generated, for example, by sensors operating in difficult environments, circuits including a full-wave rectifier and an integrator as basic components are used. A circuit of this type is used, for example, in devices for detecting pinking in Otto engines, as described, for example, in the prior patent application U.S. Ser. No. 07/592,401 filed Oct. 3, 1990 in the name of the same Applicant.
FIG. 1 of the appended drawings shows such an arrangement including a piezoelectric accelerometric sensor S whose signal is processed by a band-pass filter 1 and then by a full-wave rectifier 2 and an integrator 3 which is activated cyclically for a preset time period Ta. In this application, the signal V.sub.0 output by the integrator 3 provides information relating to the intensity of the sensor signal in the region of the resonance frequencies typical of pinking.
A typical problem in the circuit 1 to 3 of FIG. 1 is the integration of the inevitable offset voltage affecting the input signal of the integrator and of the offset voltage generated in the integrator itself, which may lead to the saturation of the output signal. This problem leads to the need to use low-offset components or to use techniques for automatically cancelling out the offset.
With reference to the circuit of FIG. 1, this can be formed by conventional circuitry with discrete components. The following, however, is concerned with solutions which enable the circuit to be produced in integrated form, specifically by CMOS technology and particularly with the use of circuitry of the type with switched capacitors.
FIG. 2 of the appended drawings shows an embodiment of the rectifier and the integrator of FIG. 1 with switched-capacitor circuitry which can be produced in integrated form. In this embodiment, the rectifier circuit 2 has an input, indicated I, and includes a circuit 10 for determining the polarity of the input signal V.sub.in and an amplifier circuit, generally indicated 11.
The polarity-determining circuit 10 comprises:
a comparator CO1, PA1 a capacitor C1 between the input terminal I and the inverting input of the comparator CO1, PA1 first and second controlled switches S1 and S2 between earth and the plate of C1 which faces the input terminal I and between the input terminal and C1, respectively, PA1 a third controlled switch S3 between the inverting input and the output of CO1, PA1 a controlled switch S10 between the output of CO1 and the input of a flip-flop circuit, generally indicated 12, whose outputs are indicated A and A. PA1 an operational amplifier A1 with its non-inverting input connected to earth, PA1 a capacitor C2 between the input terminal I and the inverting input of A1, PA1 a capacitor C3 between the inverting input and the output of A1, PA1 two controlled switches S4, S5 connected to C2, PA1 two further controlled switches S6 and S8 arranged between the input I and S4 and between I and S5, respectively, PA1 two further controlled switches S7 and S9 connected between earth and the connection between S4 and S6 and between earth and the connection between S5 and S8, respectively, PA1 two further controlled switches S12 and S13 in series and in parallel with C3 respectively, and PA1 a further controlled switch S11 between earth and the connection between C3 and S12. PA1 an operational amplifier A2 with its non-inverting input connected to earth, PA1 two capacitors C4, C5 connected between the inverting input of A2 and the output of A1 and between the inverting input and the output of A2, respectively, PA1 two controlled switches S16 and S19 in series with C5, PA1 two further controlled switches S17 and S18 in parallel between the output and the inverting input of A2, and PA1 two further controlled switches S14 and S15 between the output of A1 and C4 and between earth and the connection between S14 and C4, respectively.
In operation, the switches S1, S3 and S2, S10 respectively are piloted in an on-off manner by two clock signals, indicated, .phi..sub.1 and .phi..sub.2, which have the same frequency but are out of phase so that their respective active periods ("on" times, that is, the periods when the associated switches are closed) alternate and do not overlap, as shown by the corresponding waveforms shown in FIG. 3. As experts in the art can immediately confirm, if the input signal V.sub.in is of positive (negative) polarity, the output A of the flip-flop 12 is at level "1" ("0").
The amplifier circuit 11 comprises:
In operation, S4 and S12 are piloted by the clock or phase signal .phi..sub.1, whilst S5, S11 and S13 are piloted by the phase signal .phi..sub.2. S7 and S8 are piloted by the output A of the flip-flop 12, whilst S6 and S9 are piloted by the output A of the flip-flop.
When the input signal V.sub.in is of positive polarity, the outputs A and A of the flip-flop 12 control the switches S6, S7, S8 and S9 so that the operational amplifier A1 is connected as a non-inverting amplifier: during each "on" period of the phase signal .phi..sub.2, the capacitor C2 samples the signal V.sub.in whilst, during each of next "on" period of .phi..sub.1, it outputs its charge. When the signal V.sub.in is of negative polarity, the switches S6, S7, S8 and S9 are controlled so that the operational amplifier A1 constitutes an inverting amplifier: in this case, the capacitor C2 samples the signal V.sub.in and outputs its own charge during each "on" period of the phase .phi..sub.1.
The integrator 3 comprises:
In operation, S14 and S17 are piloted by the phase signal .phi..sub.1, whilst S15 and S16 are piloted by the phase signal .phi..sub.2. S18 and S20 are piloted by a signal R which is normally at level "one" and is at low level during the time period T.sub.a corresponding to the period during which the integrator 3 is required to integrate. This signal, like the phase signals .phi..sub.1 and .phi..sub.2, is generated by a control circuit, generally indicated CU in FIG. 2, the details of which, however, are not essential for the purposes of the present description.
An example of the waveform of R is shown in FIG. 3.
The switch S19 of the integrator 3, however, is piloted by a signal R complementary to R.
As has been seen above, in operation, the rectifier 2 outputs its signal during each "on" period of Q.sub.1 : during each of these periods, the integrator 3 zeroes its own offset voltage by means of S17 which puts A2 into the voltage-follower configuration. During each "on" period of .phi..sub.1, the integrator 3 samples the voltage output by the rectifier 2, by means of the capacitor C4. The capacitor C5 acts as the integrating and memory element. It is discharged only at the end of the integration period T.sub.a by means of the switches S18, S19, S20 which are controlled by the signals R (reset) and R (integration signal).
Obviously, the switches S19 and S16 can be replaced by a single switch controlled by the conjunction (AND) of the signals R and .phi..sub.2.
The offset voltage of A1 is cancelled out during the "on" times of Q.sub.2 by the discharge of the capacitor C3 and the connection of A1 in the "voltage-follower" configuration by means of S13.
The solution described above with reference to FIG. 2 requires a large number of components.
A first considerable simplification of the circuit is possible by incorporating the rectifier and integrator functions in the same circuit, thus eliminating an operational amplifier, as shown in FIG. 4. In this drawing, in which components described above have again been given the same reference symbols, it can be seen that the circuit 10, 12 for determining the polarity of the input signal V.sub.in remains unchanged. The full-wave rectification and the integration of the input signal, on the other hand, are achieved with the use of a single operational amplifier A1 with its associated capacitors and controlled switches. The clock signals .phi..sub.1 and .phi..sub.2, as well as the integration control signal R, retain the same waveforms, shown by way of example in FIG. 3.
The capacitor C3 acts as an integrating and memory element which is zeroed at the end of the integration period T.sub.a by means of the switches S19 and S20 piloted by the signals R and R.
The rectified and integrated signal is available at the output of the amplifier A1.
The circuit according to FIG. 4 has a much simplified structure but also has a disadvantage. In effect, the input signal V.sub.in is sampled during the "on" periods of the phase signal .phi..sub.1 or .phi..sub.2 in dependence on its polarity. This presupposes that the signal V.sub.in is always available in both the phases .phi..sub.1 and .phi..sub.2. In some applications, a useful signal is not always available throughout the clock period of the switched-capacitor system. It is thus convenient always to be able to sample the input signal in the same phase, regardless of its polarity. This would also enable the cancellation, during the other phase, of any offset voltages in the circuit upstream which generates the signal V.sub.in. This function is particularly important when signals must be integrated over long periods of time. In fact, in such cases, the minimising of the offset voltages of the input signal and of the components for processing it (amplifiers, comparators, etc.) becomes one of the main objectives for ensuring the correct operation of the device.